As illustrated in FIG. 1, a known complementary metal-oxide semiconductors (CMOS) replacement metal gate (RMG) structure includes a number of conductive layers formed on top of a high-k dielectric layer 101 on side and bottom surfaces of an n-type FET (nFET) RMG trench 103 and a p-type FET (pFET) RMG trench 105 (each formed between a pair of spacers 107 in an interlayer dielectric (ILD) 109). The spacers 107 and ILD 109 are formed above the FinFETs' source/drain regions 111 and the STI region 113. For example, a titanium nitride (TiN) layer 115 is formed over the high-k dielectric layer 101. A tantalum nitride (TaN) layer 117 is then formed over the TiN layer 115. Next, a TiN layer 119 is formed over the TaN layer 117 in the pFET RMG trench 105. The work function (WF) for the pFET RMG trench 105 is determined by the TiN layer 119. A titanium aluminum (TiAl) or titanium carbon (TiC) layer (not shown for illustrative convenience) is then formed on the bottom surface of the both RMG trenches 103 and 105. The WF for the nFET RMG trench 103 is determined by the TiAl or TiC layer. Thereafter, a Ti wetting layer (not shown for illustrative convenience) is formed on the side and bottom surfaces of the RMG trenches 103 and 105 and then both are filled with either an aluminum (Al) or tungsten (W) layer 121. Consequently, the final spacing for the Al or W layer 113 is almost diminished, particularly with respect to the pFET RMG trench 105, creating a scaling limit for the 20 nm technology node and beyond. A known chamfering technique for improving the final spacing is complicated, e.g., it requires photo-resist (litho/masking) steps, proprietary sacrificial light absorbing material (SLAM) materials, e.g., DUO, partial etching steps, etc., all of which lead to high defect levels and low yields.
A need therefore exists for methodology enabling a simpler RMG sidewall chamfering process, and the resulting device.